1. Field of the Invention
This invention relates to a method of reducing nonlinearity errors in a subranging ADC and more specifically to a method for adding a dither signal to only the ADC's fine quantizer to optimize its small signal performance.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are employed to convert "real world" signals into digital signals that are susceptible to manipulation by digital computers. In this context the term "computer" does not refer exclusively to general purpose computers, but includes special processors such as digital signal processors, vector processors, waveform encoders, etc. The most popular circuit designs for ADCs include successive-approximate, integration (single-, dual, and quad-slope, v-to-f, and .SIGMA.-.DELTA.), counter or "servo", flash and subranging types. Each approach has characteristics that make it most useful for a specific class of applications based on its linearity, absolute and relative accuracy, no-missing codes, resolution, conversion speed, stability, and price.
An ADC's linearity is measured by the deviation of its transfer function from the ideal stair-case transfer function. Ideally, the width of each output code, i.e. the quantum of analog input signal for a given digital output code, is exactly 1 least-significant bit (LSB) and the centers of each output code lie along a straight line. An ADC's differential nonlinearity (DNL) is defined as the deviation in code width from the value of 1 LSB. If DNL errors are large, the output code widths may represent excessively large and small ranges of the input signal so that one or more codes may vanish entirely. Integral nonlinearity error is the deviation of the ADC's transfer function from the straight line and represents the accumulated DNL errors. The sources of DNL and INL errors are many, but are primarily attributable to resistor and transistor gain mismatch in comparators and DACs inside the ADC.
ADCs are used in audio and video recording and transmission, in RADAR and SONAR detection and analysis, and in process monitoring and control systems, to name just a few of the myriad ADC applications. The ADC's nonlinearity errors tend to repeat in response to an analog input signal, and thus produce spurs in its frequency response that distort the signal. Because the spurs tend to lie very close to the signal frequency, it is difficult and expensive to remove them using conventional filtering techniques. The most widely used approach to improve linearity is to laser trim the ADC's bias resistors to correct mismatch, and thus reduce the DNL and INL errors directly.
Another approach, as described by Manfred Bartz, Hewlett-Packard Journal, December 1993, pp. 44-45, is to add a dither signal to the analog input signal and subtract its digital equivalent from the output of the ADC. This randomizes the ADC's nonlinear quantization errors and thus distributes them throughout its frequency response, reducing or eliminating the spurs, without degrading the overall SNR.
The degree of improvement is directly related to the magnitude of the dither signal; the larger the dither signal the greater the randomization of the quantization errors. However, if the analog input signal varies over the full-scale input range of the ADC, a dither signal greater than 1 LSB may saturate the ADC thereby lowering the overall SNR. As a practical matter, the analog input signal must be constrained to be no greater than mid-scale to realize any significant benefit from dithering. This effectively wastes one bit of resolution. Furthermore, the dither circuitry is external to the ADC, and thus will not track processing variations or temperature changes.
Flash and subranging ADCs are discussed by Paul Horowitz, Winfield Hill, The Art of Electronics, Cambridge University Press, New York, 1989, pages 621 and 622. The highest conversion rates are attainable using a single N-bit flash quantizer that has 2.sup.N -1 comparators biased 1 LSB apart using a resistive ladder. As the input increases, it causes an increasing number of comparators to switch states. The outputs of the comparators are applied to a logic encoder, which can implement any one of several encoding schemes, including offset binary, 2's complement, sign magnitude, Gray code and binary-coded-decimal (BCD). The great advantage of a flash converter is that the only delays encountered in the conversion process are those attributable to the ladder/comparator stage and to the encoder. However, a high resolution flash ADC is not cost or space efficient due to the enormous number of resistors and comparators.
For these reasons, the flash ADC architecture is employed as a component in a subranging ADC, which capitalizes on the flash ADC's speed but also substantially reduces the number of components. A subranging ADC captures an analog signal using a sample and hold circuit that couples the "held" signal to a course (L-bit) flash-quantizer and a summing amplifier. The course quantizer provides a digital signal to a DAC which "reconstructs" the original analog input signal. The summing amplifier subtracts the reconstructed signal from the held input signal, gains up the residual and feeds it to a fine M-bit flash-quantizer, which converts the residual signal to provide the least significant bits of the subranging ADC. An extra bit(s) is provided in the fine-quantizer to provide an "overlap" that compensates for the quantization level error in the coarse quantizer. To achieve the same resolution as a single N-bit flash quantizer with one overlap bit, the coarse and fine quantizer bit rates satisfy L+M-1=N.
The subranging ADC may exhibit significant nonlinearity errors, which are attributable to its parallel architecture that requires a relatively large number of matched resistors and comparators as compared to other ADC types. Typically, the resistor values are laser trimmed as described above. If Hewlett-Packard's external dithering circuitry were connected around a subranging ADC, the dither signal would randomize the quantization errors in both the coarse and fine quantizers as well as the nonlinear errors in the other circuit components. However, in order to add enough noise to realize these benefits the input signal would have to be constrained to be less than mid-scale of the coarse quantizer. Furthermore, the discrete dithering circuit and ADC would not track processing and temperature variations. Most importantly, the nonlinear errors in the external DAC are gained up by the summing amplifier. This additional noise is significant, and will severely degrade the overall noise figure and SNR of the subranging ADC, especially for small input signals.